1--Field of the Invention
This invention relates to a circuit for managing numbers of accesses to logic resources thereby deriving write addresses of available resources in a set of logic resources in dependence on the numbers of accesses updated, the number of accesses attributed to a logic resource being decremented by one unity in response to a read address of said resource.
For example, logic resources are data cells of a memory which is used in a time switching system and in which data received randomly are written.
2--Description of the Prior Art
The U.S. Pat. No. 4,884,264 divulges a system for switching data blocks between plural incoming time division multiplex ways and plural outgoing time division multiplex ways. The blocks in each of the multiplex ways can be synchronous blocks in circuit-mode and/or asynchronous blocks in packet-mode, and have a constant length.
In particular the asynchronous blocks in the same communication are transmitted sporadically in the multiplex ways.
All the data blocks are written progressively with their arrival into a buffer memory and are read-out one or several times from the buffer memory so as to be diffused to one or several outgoing multiplex ways. In effect, the communication relating to data blocks in an incoming way can be a point-to-point communication or a multipoint communication. For a multipoint communication a data block must be read in the buffer memory s many times as there are addressee outgoing multiplex ways which should receive the data block. The buffer memory cell in which a data block is written must be released on the last read of the block.
As embodied by this invention the logic resources can thus be data block cells of the buffer memory, and the number of accesses to a resource designates the number of read-outs or number of outgoing multiplex ways to which a data block stored in the resource must be diffused.
Aware that firstly, the data blocks are written sporadically in the buffer memory, secondly a data block must remain in the buffer memory during several read-out cycles in order to be diffused, U.S. Pat. No. 4,884,264 proposes an access number managing circuit, referred to as a "buffer memory" managing and write addressing circuit" so as to optimize the capacity of the buffer memory whilst managing it, i.e., updating the numbers of accesses progressively as data blocks are diffused.
This managing circuit is basically organized around two memories, each memory containing cells respectively associated to those of the buffer memory.
A first memory, referred to as a "cell release memory", stores the updated numbers access. Initially, when a data block is written-in, a cell in the first memory stores the number of accesses to which the block should be transmitted, then on each time this block is read-out, the number of accesses is decremented by unity until it reaches zero so as to release the associated cell in the buffer memory for writing another block.
In order to update each access number, the data outputs and inputs of the first memory are linked through a decrementation circuit and a zero test circuit, and the first memory is associated to other multiplexers and logic gates for its write-in and read-out addressing as a function of the write-in and read-out times of the buffer memory cells notably.
The second memory referred to as an "available cell address memory", forms a circuit for memorizing logic resource availability conditions, i.e., block cell conditions in the buffer memory, and for deriving free cell addresses. This circuit is described in the European patent application No. 298,793. The second memory basically comprises a matrix of one-bit cells, and a buffer memory cell address encoding circuit. The cells of the matrix are respectively assigned to the block cells of the buffer memory. Each matrix cell memorize an availability condition bit of the respective cell of the buffer memory. The condition bit is at high state "1" when the buffer memory cell is free and is thus ready to store a data block from an incoming multiplex way. The condition bit is at low state "0" when the buffer memory cell is occupied by a written data block which is to be read-out one or several times depending on the respective updated number of accesses memorized in the first memory. The encoding circuit in the second memory is connected to the outputs of all the cells of the matrix so as to select one of the cells of the matrix having a free condition bit "1", according to a predetermined cell priority order, and thus permanently derive the address of a free matrix cell selected equal to the write address of the respective block cell in the buffer memory.
Apart from the decrementation circuit and the zero test circuit, other logic means between the data output of the first memory and the data input of the second memory are provided in the managing circuit so as to modify the condition bits in the second memory. In fact, on reading a data block, only the corresponding cell in the first memory is read-out and write-in addressed to decrement the number of accesses by one unity as long as it is different from zero, the bit at the low state in the corresponding cell of the second memory not being modified. Conversely, when the number of accesses reaches zero, after the last data block read-out, the decrementation circuit requests modification of the condition bit in the second memory.
The material separation of the update of access numbers essentially made by the first memory and of the monitoring of the availability conditions of the logic resources made by the second memory is thus restrictive both from the point of view of the time to perform this operations which depend on the numerous circuits implemented, and the point of view of the cumbersomeness of the different circuits and memories.